1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor device including an electrical fuse.
2. Description of the Related Art
Semiconductor memory devices such as a Dynamic Random Access Memory (DRAM) device generally use electrical fuses to protect against bit failures that may frequently occur after packaging. For such purposes, a semiconductor memory device uses a number of electrical fuses equal to the number of bits in a fail address (that is, the address of a failed memory/erroneous memory).
FIG. 1 is a block diagram illustrating a conventional semiconductor device capable of saving 1 bit of data. Here, for illustration purposes, it is assumed that the address corresponding to the memory space for storing the 1 bit data is formed of four bits.
Referring to FIG. 1, the semiconductor device 10 includes a shifting unit 11, a latch unit 13, and a fuse unit 15. The shifting unit 11 sequentially generates first to fourth rupture enable signals EN1 to EN4 in response to an initialization signal RST, a rupture source signal SOUR, and a shifting control signal CMD. The latch unit 13 individually latches the four repair target address bits A1 to A4 in response to a latch control signal STOREP. The fuse unit 15 outputs four programmed address bits RA1, RA2, RA3 and RA4 that correspond to the four repair target address bits A1 to A4 and are programmed in response to the first to fourth rupture enable signals EN1 to EN4 and four latch address bits AQ1 to AQ4 that are outputted from the latch unit 13.
The semiconductor device 10 having the above-described structure may have a memory storage capacity of one bit. Hereinafter, a semiconductor device having a memory storage capacity of two bits is illustrated.
FIG. 2 is a block diagram illustrating a conventional semiconductor device having a memory storage capacity of two bits.
Referring to FIG. 2, the semiconductor device 20 includes a shifting unit 21, a latch unit 23, a first fuse unit 25, and a second fuse unit 27. The shifting unit 21 sequentially generates first to eighth rupture enable signals EN1 to EN8 in response to an initialization signal RST, a rupture source signal SOUR, and a shifting control signal CMD. The latch unit 23 individually latches the four bits A1 to A4 of a first repair target address and the four bits B1 to B4 of a second repair target address in response to a latch control signal STOREP. The first fuse unit 25 outputs four first programmed address bits RA1, RA2, RA3 and RA4 that correspond to the four first repair target address bits A1 to A4 and are programmed in response to the first to fourth rupture enable signals EN1 to EN4 and four first latch address bits AQ1 to AQ4 that are outputted from the latch unit 23. The second fuse unit 27 outputs four second programmed address bits RB1, RB2, RB3 and RB4 that correspond to the four second repair target address bits B1 to B4 and are programmed in response to the fifth to eighth rupture enable signals EN5 to EN8 and four second latch address bits BQ1 to BQ4 that are outputted from the latch unit 23.
The semiconductor devices 10 and 20 having the above-described structure may sequentially program the programmed address RB1, RB2, RB3 and RB4 that corresponds to the repair target address A1 to A4 or B1 to B4 easily by using the shifting unit 11 or 21 that receives a shifting control signal CMD which toggles.
The semiconductor devices 10 and 20 having the above-described structure occupy more and more space as the memory storage capacity becomes greater. More specifically, the number of bits of the repair target address A1 to A4 or B1 to B4 is increased as the memory storage capacity is increased. Also, since the multiple rupture enable signals EN1 to ENK, where K is a multiple of ‘4’, is to be sequentially generated according to the increasing number of bits of the repair target address A1 to A4 or B1 to B4, the number of shift registers included in the shifting unit 11 or 21 is increased in proportion as well. Therefore, the conventional semiconductor devices 10 and 20 have increased circuit spaces according to the number of circuits, e.g., shift registers, that increases in proportion to the increase in the memory storage capacity.